The present invention relates generally to semiconductor manufacturing and, more particularly, to forming fins in FinFET devices.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the principles of the invention form a fin structure in a FinFET device. The fin structure is formed in the shape of a xe2x80x9cTxe2x80x9d through the use a selective etching process. The T-shaped fin structure allows a greater portion of the gate material to interface with the fin structure thereby improving device performance.
In accordance with the purpose of this invention as embodied and broadly described herein, a semiconductor device includes a substrate, an insulating layer formed on the substrate, a fin structure having a T-shaped cross-section that is formed on a portion of the insulating layer, and a gate formed on the insulating layer and surrounding the T-shaped fin structure.
In another implementation consistent with the present invention, a method for forming a fin structure in a FinFET device is provided. The method includes forming a first dielectric layer on a silicon-on-insulator (SOI) wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate, etching the first dielectric layer, and etching the silicon layer to form a T-shaped fin structure, where the etching includes a first etch, a second etch, and a third etch.
In yet another implementation consistent with the principles of the invention, a method for forming a fin structure on a SOI wafer that includes a silicon layer on an insulating layer that is formed over a semiconductor substrate is provided. The method includes etching the silicon layer using a first etch procedure, etching, following the first etch procedure, the silicon layer using a second etch procedure, and etching, following the second etch procedure, the silicon layer using a third etch procedure to form a T-shaped fin structure.